Research on Si and SiGe junctionless bulk FinFETs utilizing junctionisolation scheme and temperature-dependent transistor characteristics

Abstract

A Si and SiGe-channel junctionless-accumulation-mode (JAM) PMOS bulk FinFETs were successfully demonstrated on Si substrate with PN junction-isolation scheme for the first time. The Si and SiGe channel JAM bulk FinFETs with fin width of 18 nm exhibits excellent subthreshold characteristics such as subthreshold swing of 68 and 64 mV/decade, drain-induced barrier lowering (DIBL) of 9mV/V and 40 mV/V and high $I_{on}/I_{off}$ current ratio ($~ 1×10^7 and ~ 1×10^6$). The SiGe channel JAM FET’s change of substrate bias from 0 V to 5 V leads to the threshold voltage shift of 53 mV by modulating the effective channel thickness. When compared to the Si-channel bulk FinFETs with fin width of 18 nm, Si and SiGe channel devices exhibits comparable subthreshold swing and DIBL. For devices with longer fin width, SiGe channel devices exhibits much lower DIBL, indicating superior top-gate controllability and robustness to substrate bias compared to the Si channel devices. Parasitic bipolar junction transistor (BJT)-induced steep slope (less than 60 mV/dec.) was observed under high drain voltage at room temperature. A zero temperature coefficient point was observed in the transfer curves as temperature increases from -120°C to 120°C, confirming that mobility degradation is dominantly affected by phonon scattering mechanism. Lastly, high temperature measurement with high drain voltage suggests decrease in impact ionization ratio due to energy loss from increased phonon scattering.