Research on improvement of electrical properties of Ge pMOS devices using Vacuum Annealing and Ultrathin Hf layer with sub-1nm EOT

Abstract

In this thesis, gate formation methods using Vacuum Annealing (VA) and ultrathin metal capping layers (Al, Hf and Zr) prior to the deposition of high-κ dielectrics (HfO2 and ZrO2) were studied and analyzed. Improvements in electrical parameters for HfO2/Hf-capped/VA gate stacks when compared to HfO2-alone stacks were achieved. EOT scaling was also experimented with the same gate stacks. As a result, germanium pMOS gate stack fabricated with vacuum annealing, ultrathin (~0.5 nm) Hf capping and deposition of HfO2 (~2.5 nm) exhibited the best values of ΔVFB = 78.04 mV, Jg = 9.28×10-3 A/cm2 (@|VG-VFB| = 1 V) at EOT = 0.62 nm. TEM, XPS and SIMS were used in search for the cause of the improvements in the electrical performances. Ge outdiffusion which causes degradation of high-κ dielectric (HfO2) was found. Such result suggests that suppression of incorporation of Ge atoms into the high-κ dielectric layers is important for aggressive EOT scaling of MOS devices. Ge atoms diffuse into the gate dielectric layer in the form of gaseous GeO at temperatures higher than 400 ℃. Vacuum Annealing the Ge surface removed the native GeOx and ultrathin Hf capping layer prevented GeO volatilization from the interface. Even without VA step, Hf capping layer cut the C-V hysteresis by more than half when compared to the HfO2-alone samples.