Three integer multiplication based complex constant multiplier for multipath pipelined 128-point FFT processors

Abstract

Multi-input Multi-output Orthogonal Frequency Division Multiplexing (MIMO OFDM) is widely used in wireless communication systems. In Ultra Wideband (UWB) mainly applied in the Wireless Personal Area Network (WPAN) 802.15 3c standard, MIMO OFDM is an important way in modulation. And in MIMO OFDM, Fast Fourier Transform (FFT) is a key element, since the computational complexity of FFT processor is very high in the whole system. In this thesis, the three integer multiplication based complex constant multiplier is applied in the four path pipelined 128 point FFT to reduce the computational complexity and the area, an important Intellectual Property (IP) in VLSI design. Since the number of the multipliers decreased from 4 to 3 in a complex multiplication, the computation is compensated by the increase of adders from two to three and extra multiplexers. Though the result is not as much as 25% as expected, the area reduced by 19% and 8% respectively in 4-path pipelined 128 point FFT compared to two previous architectures, the pool-based and the path-based architectures, with Multiple Radix Multipath Delay Feedback (MRMDF).