Proposal of TSV-based 3D clock distribution networks and analysis관통 실리콘 비아 기반 3차원 클락 분배망에 관한 연구

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dc.contributor.advisorKim, Joung-Ho-
dc.contributor.advisor김정호-
dc.contributor.authorKim, Da-Young-
dc.contributor.author김다영-
dc.date.accessioned2015-04-23T06:14:08Z-
dc.date.available2015-04-23T06:14:08Z-
dc.date.issued2012-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=567281&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/196717-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2012.8, [ v, 45 p. ]-
dc.description.abstractIn recent years, as density of integrated circuit increases, it is changing quickly from two-dimensional to three-dimensional. A major current focus in three-dimensional integrated circuit (3D IC) is how to connect chips vertically. Among vertical interconnection technologies such as bond wire, flip chip, and through silicon via (TSV), the TSV is a remarkable technology to achieve a high level in not only the degree of integration but also electrical performance. Moreover, as digital systems speed gets higher, the timing margin becomes much tighter. Then, the clock signal which is a timing reference for the operation of systems critically affects to the performance of synchronous digital systems. That is, it is important for the clock signal to be distributed with low skew and low jitter. Much research has focused on low skew and low jitter clock distribution network (CDN) in two-dimensional integrated circuits. However the CDN in TSV-based 3D IC has not been studied yet, thus the 3D CDN in TSV-based 3D IC is strongly needed. In addition, low power consumption technology is major issue in semiconductor industry. However the amount of consumed power due to clock signal severely increases as the operating frequency increases. That is, the power consumption is also critical to system performance. The technology of 3D IC is developed due to the high density. That is, the reduction of the area consumption is becoming important in 3D IC. The interconnection metal for using the transmission of the clock signal occupies a lot portion of the on-chip area, so minimizing area consumption of CDN affects the whole area consumption. Thus, as systems become smaller and have more functions, it takes considerable effort to reduce the size of the CDN. For this reason, area consumption is also needed as the performance evaluation factor of CDN. Hence, new 3D CDN schemes for TSV-based 3D IC are proposed by considering skew, jitter, power consumption and area con-sumption. The 3-t...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subject3D Clock Distribution Network (3D CDN)-
dc.subject면적 소모-
dc.subject전력 소모-
dc.subject지터-
dc.subject스큐-
dc.subject3차원 집적회로-
dc.subjectThrough Silicon Via (TSV)-
dc.subject3D IC-
dc.subjectSkew-
dc.subjectJitter-
dc.subjectPower Consumption-
dc.subjectArea Consumption-
dc.subject3차원 클락 분배망-
dc.subject관통 실리콘 비아-
dc.titleProposal of TSV-based 3D clock distribution networks and analysis-
dc.title.alternative관통 실리콘 비아 기반 3차원 클락 분배망에 관한 연구-
dc.typeThesis(Master)-
dc.identifier.CNRN567281/325007 -
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid020104261-
dc.contributor.localauthorKim, Joung-Ho-
dc.contributor.localauthor김정호-
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EE-Theses_Master(석사논문)
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