Analysis and minimization of power in mesh clock network

Abstract

Mesh clock network is very effective at reducing clock skew. So mesh clock network has been widely used in high performance processor designs for smaller skew. But mesh clock network causes a large increases of power consumption due to additional redundant wire capacitance and shorted buffers. In this thesis, I propose the power minimization method in mesh clock network. This thesis first analyzes the short-circuit power consumption of the mesh clock network. I then propose a new clock buffer, which practically eliminates short-circuit current in a mesh clock network. Practical design methodology of mesh clock network including the method to determine the number of mesh grid and to synthesis of premesh tree using proposed clock buffer is also proposed.