Design of a high-throughput and area-efficient SHA-2 hardware for SSDs

Abstract

As the data deduplication system has received attention as a promising solution to enhance reliability in Solid State Drives (SSDs), a cryptographic hash function SHA-2 that is used for detecting data duplication is the key bottleneck because of the overhead of extra calculation. Therefore, a dedicated hardware for cryptographic hash function is commonly used to speed up calculation and minimize the performance degradation of SSDs. As a result, the importance of high-performance SHA-2 implementation has been enlarged. In this thesis, an optimized architecture for increasing throughput is proposed by minimizing critical path delay of iterative calculation that is a major burden of delay to support high data rate of SSDs. In addition, a technique for reducing the required area of SHA-2 by computing two iterative calculations in a single cycle is proposed. Synthesis result shows that the proposed architecture increases throughput up to 6Gbps or more compared to conventional techniques used for high throughput and the required area is reduced by 41%.