Design of system and intra-panel interface for display devices디스플레이 기기를 위한 시스템 인터페이스와 패널 내부 인터페이스의 설계

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dc.contributor.advisorKim, Lee-Sup-
dc.contributor.advisor김이섭-
dc.contributor.authorWon-Young, Lee-
dc.contributor.author이원영-
dc.date.accessioned2015-04-23T06:12:24Z-
dc.date.available2015-04-23T06:12:24Z-
dc.date.issued2012-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=568090&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/196520-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2012.2, [ x, 82 p. ]-
dc.description.abstractDisplay interface is typically composed of two interfaces in the data communication from a PC or a TV to another display device. First, it is called ‘System interface’ that the data communication from a process unit which makes visual data to a display device. Nowadays as the demands for 3-D display, high resolution TV and monitors increase, the amount of the transmitted visual data is also gradually increased. Conventional display interfaces such as DVI (Digital visual interface) and VGA (Video graphics array), however, has a limit to handle various demands. Therefore, the next generation system interfaces such as HDMI and DisplayPort have been released and these high performance interfaces can support the maximum data rate of tens of Gb/s through cables. In this thesis, A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme has been presented as a precedent study on DisplayPort version 1.2. The proposed scheme enables the CDR circuit to change an operation mode without output phase noise degradation as well as a stability problem. The measured rms jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps smaller as compared with the conventional CDR circuit. After the precedent study, A 5.4/2.7/1.62 Gb/s multi-rate receiver has been designed for DisplayPort version 1.2. This receiver adopts an adaptive loop bandwidth calibration scheme and includes a dual-mode phase detector and a bandwidth controllable equalizer. A dual-mode binary phase detector and a bandwidth controllable equalizer are proposed for enabling the multi-rate operation of the receiver with the optimization of design complexity. A voltage booster is also proposed for an active inductor to achieve the bandwidth extension with low power consumption. The proposed circuit recovers data and clock with quarter/half-rate operations with the peak to peak clock jitter of 29.9/39.8/43.3 ps and rms jitter of 3.215/4.077/4.828 ps for 5.4/2.7/1.62 Gb/s data rates, r...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subject디스플레이 인터페이스-
dc.subjectSimultaneous Switching Noise-
dc.subjectChip-On-Glass-
dc.subjectClock and Data Recovery-
dc.subjectEqualizer-
dc.subjectDisplay Interface-
dc.subject등화기-
dc.subject클럭 데이터 복구-
dc.subject칩 온 글라스-
dc.subject동시 스위칭 잡음-
dc.titleDesign of system and intra-panel interface for display devices-
dc.title.alternative디스플레이 기기를 위한 시스템 인터페이스와 패널 내부 인터페이스의 설계-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN568090/325007 -
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid020085143-
dc.contributor.localauthorKim, Lee-Sup-
dc.contributor.localauthor김이섭-
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EE-Theses_Ph.D.(박사논문)
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