DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Cho, Seong-Hwan | - |
dc.contributor.advisor | 조성환 | - |
dc.contributor.author | Kim, Kwang-Seok | - |
dc.contributor.author | 김광석 | - |
dc.date.accessioned | 2015-04-23T06:12:18Z | - |
dc.date.available | 2015-04-23T06:12:18Z | - |
dc.date.issued | 2013 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=566034&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/196509 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2013.8, [ vii, 52 p. ] | - |
dc.description.abstract | Time-to-digital converter (TDC) has become increasingly more important with the advent of digital-friendly mixed-signal and analog circuits such as all-digital PLL/DLLs and time-domain ADCs. In a all-digital PLL(ADPLL) and a time-domain ADC, many analog-intensive circuits are replaced by TDC and digital intensive circuits. These circuits are well suited for nanometer CMOS technology, and even can be synthesis like digital circuits. Compared with a ADC, a TDC quantizes input time-signal and conducts signal processing in time-domain, which has benefits from nano-scale CMOS technology with fast transition but low supply voltage. In order to improve the performance of digital-friendly mixed-signal and analog circuits, much effort was put into improving the TDC’s time resolution to below sub-gate delay and conversion rate to above tens of Msps, resulting in a high-speed and high-resolution TDC. Recent innovations in achieving high-speed and high-resolution TDC include time-amplifiers (TAs). The function of TA is same as the amplifier in voltage-domain, amplifying small time-input with large enough to process further. Using these TAs, two-step, pipelined, and cyclic TDC are introduced. However, the gain of these TAs is unpredictable due to meta-stability and thus requires calibration for improved linearity. Although there exists a TA that does not use meta-stability but use different propagation delay in variable delay cells, it still suffers from linearity and requires calibration. Employing these time-amplifiers (TAs), many TDCs have recently been proposed, such as two-step [22,29], cyclic [25], and asynchronous pipeline [30] TDCs. While these methods look to mimic the operations of their ADC counterparts, a critical flaw is that register in time- domain is absent and thus pipelining cannot be achieved. For example, [21-29] are all based on an asynchronous operation, where input propagates through the delay cells without being stopped and thus they cannot operate ... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Time-to-Digital Converter(TDC) | - |
dc.subject | 시간 저장기 | - |
dc.subject | 2.5b/스테이지 | - |
dc.subject | 파이프라인 | - |
dc.subject | 시간 기반 전압 디지털 변환기 | - |
dc.subject | 위상 고정 루프와 디지털 위상 고정 루프 | - |
dc.subject | Time Amplifier | - |
dc.subject | Time Register | - |
dc.subject | Two-step Architecture | - |
dc.subject | PLL and all-digital PLL(ADPLL) | - |
dc.subject | Time-domain ADC | - |
dc.subject | Pipeline | - |
dc.subject | 2.5b/stage | - |
dc.subject | Time storage | - |
dc.subject | 시간 디지털 변환기 | - |
dc.subject | 시간 증폭기 | - |
dc.subject | 시간 레지스터 | - |
dc.subject | 투스텝 구조 | - |
dc.title | Design of high-speed and high-resolution time-to-digital converter using time arithmetic circuits | - |
dc.title.alternative | 시간 연산 회로를 이용한 고속 고해상도 시간 디지털 변환기의 설계 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 566034/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
dc.identifier.uid | 020107103 | - |
dc.contributor.localauthor | Cho, Seong-Hwan | - |
dc.contributor.localauthor | 조성환 | - |
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