Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache

Abstract

Nonvolatile memory such as magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with SRAM. 3-D integration technology using through-silicon vias enables stacking disparate memory technologies (e. g., SRAM and MRAM) together onto chip-multiprocessors (CMPs). The use of hybrid memories as an on-chip cache can take advantage of the best characteristics that each technology offers. However, the inherent high power density and heat removal limitation in 3-D integrated circuits may incur temperature-related problems. In this paper, we propose a runtime thermal management method for CMPs with the 3-D stacked hybrid SRAM/MRAM L2 cache. The proposed method combines dynamic cache management such as resource allocation, way-based power gating, and data migration with dynamic voltage and frequency scaling of processing cores in a temperature- and energy-aware manner. Experimental results show that the proposed runtime method with the 3-D stacked hybrid L2 cache offers up to 107.37% (55.28% on average) performance improvement and 88.47% (47.65% on average) energy efficiency improvement compared with existing thermal management methods with 3-D stacked SRAM-based L2 cache.