A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design

Abstract

This paper proposes a replica-driving technique that can be applied to implement low-power high-performance switched-capacitor (SC) amplifiers. The reduced swing range problem arising from the output-stage source-follower is resolved by a simple SC level shifter, without additional supply or static buffer. The output driving capability is enhanced by using a capacitively-controlled class-AB output stage. Owing to the high-speed open-loop output driving, the reference driver does not require any bypass capacitor. A prototype 12 bit 150 MS/s pipelined ADC was designed for concept proof in a 65 nm CMOS process. The ADC core consumes 75.6 mW at a 1.2 V supply. The measured DNL and INL are 0.5 LSB and 1.5 LSB, respectively. The SNDR and SFDR are 58.2 dB and 73.6 dB at 150 MS/s with an 8.3 MHz input.