DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lakshminarayana, Nagesh B. | ko |
dc.contributor.author | Lee, Jaekyu | ko |
dc.contributor.author | Kim, Hyesoon | ko |
dc.contributor.author | Shin, Jinwoo | ko |
dc.date.accessioned | 2014-11-25T09:32:01Z | - |
dc.date.available | 2014-11-25T09:32:01Z | - |
dc.date.created | 2013-11-21 | - |
dc.date.created | 2013-11-21 | - |
dc.date.created | 2013-11-21 | - |
dc.date.created | 2013-11-21 | - |
dc.date.issued | 2012-07 | - |
dc.identifier.citation | IEEE COMPUTER ARCHITECTURE LETTERS, v.11, no.2, pp.33 - 36 | - |
dc.identifier.issn | 1556-6056 | - |
dc.identifier.uri | http://hdl.handle.net/10203/191183 | - |
dc.description.abstract | GPGPU architectures (applications) have several different characteristics compared to traditional CPU architectures (applications): highly multithreaded architectures and SIMD-execution behavior are the two important characteristics of GPGPU computing. In this paper, we propose a potential function that models the DRAM behavior in GPGPU architectures and a DRAM scheduling policy, alpha-SJF policy to minimize the potential function. The scheduling policy essentially chooses between SJF and FR-FCFS at run-time based on the number of requests from each thread and whether the thread has a row buffer hit. | - |
dc.language | English | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.title | DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function | - |
dc.type | Article | - |
dc.identifier.wosid | 000312559500002 | - |
dc.identifier.scopusid | 2-s2.0-84870990602 | - |
dc.type.rims | ART | - |
dc.citation.volume | 11 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 33 | - |
dc.citation.endingpage | 36 | - |
dc.citation.publicationname | IEEE COMPUTER ARCHITECTURE LETTERS | - |
dc.identifier.doi | 10.1109/L-CA.2011.32 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Shin, Jinwoo | - |
dc.contributor.nonIdAuthor | Lakshminarayana, Nagesh B. | - |
dc.contributor.nonIdAuthor | Lee, Jaekyu | - |
dc.contributor.nonIdAuthor | Kim, Hyesoon | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | GPGPU | - |
dc.subject.keywordAuthor | DRAM scheduling | - |
dc.subject.keywordAuthor | Potential function | - |
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