DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Youngjoo | ko |
dc.contributor.author | Yoo, Hoyoung | ko |
dc.contributor.author | Yoo, Injae | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.date.accessioned | 2014-09-01T08:15:45Z | - |
dc.date.available | 2014-09-01T08:15:45Z | - |
dc.date.created | 2014-07-08 | - |
dc.date.created | 2014-07-08 | - |
dc.date.issued | 2014-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.5, pp.1183 - 1187 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/189433 | - |
dc.description.abstract | This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm(2). | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CHIP | - |
dc.title | High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives | - |
dc.type | Article | - |
dc.identifier.wosid | 000337159500023 | - |
dc.identifier.scopusid | 2-s2.0-84899855190 | - |
dc.type.rims | ART | - |
dc.citation.volume | 22 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 1183 | - |
dc.citation.endingpage | 1187 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2013.2264687 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | BCH code | - |
dc.subject.keywordAuthor | circuit optimization | - |
dc.subject.keywordAuthor | digital integrated circuits (ICs) | - |
dc.subject.keywordAuthor | flash memory | - |
dc.subject.keywordAuthor | VLSI | - |
dc.subject.keywordPlus | FLASH MEMORIES | - |
dc.subject.keywordPlus | CHIP | - |
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