DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Daejin | ko |
dc.contributor.author | Kim, Tag-Gon | ko |
dc.date.accessioned | 2014-09-01T08:15:05Z | - |
dc.date.available | 2014-09-01T08:15:05Z | - |
dc.date.created | 2014-07-17 | - |
dc.date.created | 2014-07-17 | - |
dc.date.issued | 2014-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.5, pp.1187 - 1191 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/189426 | - |
dc.description.abstract | The bit-line sense amplifier (S/A) for on-chip flash memory compares cell current with reference current to identify data that are programmed. The S/A for 0 (erased) cell data consumes a large sink current, which is greater than off-current for 1 (programmed) cell data. This brief proposes a built-in write/read path based on binary inversion methods to reduce the sensing current of S/A. An original binary code is programmed into flash memory with an inverted binary code based on the proposed bit inversion techniques. The de-inversion hardware, which is implemented with small logic gates to restore original binary data, only consumes logic current instead of analog sink current in the S/A. The proposed techniques are evaluated for the DSPStone benchmark and are applied to the modified S/A for ARM Cortex-M3-based microcontroller with 128-kB on-chip flash memory based on a 0.18-um EEPROM technology. The circuit-level simulation result for the DSPStone benchmark shows that a newly implemented chip with the S/A based on the proposed technique consumes approximately less than 22% of the operating power that conventional S/A uses. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Built-In Binary Code Inversion Technique for On-Chip Flash Memory Sense Amplifier With Reduced Read Current Consumption | - |
dc.type | Article | - |
dc.identifier.wosid | 000337159500024 | - |
dc.identifier.scopusid | 2-s2.0-84899985342 | - |
dc.type.rims | ART | - |
dc.citation.volume | 22 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 1187 | - |
dc.citation.endingpage | 1191 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2013.2265894 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, Tag-Gon | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Bit-line sense amplifier | - |
dc.subject.keywordAuthor | data-pattern-dependent sensing | - |
dc.subject.keywordAuthor | flash memory | - |
dc.subject.keywordAuthor | low dynamic power | - |
dc.subject.keywordAuthor | read-path | - |
dc.subject.keywordAuthor | sense circuit | - |
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