DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, W. | ko |
dc.contributor.author | Ryu, C. | ko |
dc.contributor.author | Park, J. | ko |
dc.contributor.author | Kim, Joungho | ko |
dc.date.accessioned | 2010-05-31T08:51:14Z | - |
dc.date.available | 2010-05-31T08:51:14Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2008-05-19 | - |
dc.identifier.citation | 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.427 - 430 | - |
dc.identifier.uri | http://hdl.handle.net/10203/18681 | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE | - |
dc.title | Jitter suppressed on-chip clock distribution using package plane cavity resonance | - |
dc.type | Conference | - |
dc.identifier.wosid | 000258515300108 | - |
dc.identifier.scopusid | 2-s2.0-51749092886 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 427 | - |
dc.citation.endingpage | 430 | - |
dc.citation.publicationname | 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008 | - |
dc.identifier.conferencecountry | SI | - |
dc.identifier.conferencelocation | Suntec | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, Joungho | - |
dc.contributor.nonIdAuthor | Lee, W. | - |
dc.contributor.nonIdAuthor | Ryu, C. | - |
dc.contributor.nonIdAuthor | Park, J. | - |
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