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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

A 9b, 1.12ps Resolution 2.5b/Stage Pipelined Time-to-Digital Converter in 65nm CMOS Using Time-Register

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dc.contributor.authorKim, KwangSeokko
dc.contributor.authorYu, Wonsikko
dc.contributor.authorCho, SeongHwanko
dc.date.accessioned2013-12-06T01:09:19Z-
dc.date.available2013-12-06T01:09:19Z-
dc.date.created2013-10-03-
dc.date.created2013-10-03-
dc.date.issued2013-06-13-
dc.identifier.citation2013 IEEE Symposia on VLSI Technology and Circuits, pp.136 - 137-
dc.identifier.urihttp://hdl.handle.net/10203/182716-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleA 9b, 1.12ps Resolution 2.5b/Stage Pipelined Time-to-Digital Converter in 65nm CMOS Using Time-Register-
dc.typeConference-
dc.identifier.scopusid2-s2.0-84883798275-
dc.type.rimsCONF-
dc.citation.beginningpage136-
dc.citation.endingpage137-
dc.citation.publicationname2013 IEEE Symposia on VLSI Technology and Circuits-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationKyoto-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorCho, SeongHwan-
dc.contributor.nonIdAuthorKim, KwangSeok-
dc.contributor.nonIdAuthorYu, Wonsik-
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