DC Field | Value | Language |
---|---|---|
dc.contributor.author | Insup Shin | ko |
dc.contributor.author | Jae-Joon Kim | ko |
dc.contributor.author | Jae-Joon Kim | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.date.accessioned | 2013-12-06T01:05:20Z | - |
dc.date.available | 2013-12-06T01:05:20Z | - |
dc.date.created | 2013-10-02 | - |
dc.date.created | 2013-10-02 | - |
dc.date.issued | 2013-09-05 | - |
dc.identifier.citation | International Symposium on Low Power Electronics and Design, pp.199 - 204 | - |
dc.identifier.uri | http://hdl.handle.net/10203/182654 | - |
dc.language | English | - |
dc.publisher | International Symposium on Low Power Electronics and Design | - |
dc.title | A pipeline architecture with 1-cycle timing error correction for low voltage operations | - |
dc.type | Conference | - |
dc.identifier.wosid | 000337238700034 | - |
dc.identifier.scopusid | 2-s2.0-84889597890 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 199 | - |
dc.citation.endingpage | 204 | - |
dc.citation.publicationname | International Symposium on Low Power Electronics and Design | - |
dc.identifier.conferencecountry | CC | - |
dc.identifier.conferencelocation | Bejing, China | - |
dc.identifier.doi | 10.1109/ISLPED.2013.6629294 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.contributor.nonIdAuthor | Insup Shin | - |
dc.contributor.nonIdAuthor | Jae-Joon Kim | - |
dc.contributor.nonIdAuthor | Jae-Joon Kim | - |
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