Energy-aware dynamic reconfiguration of 3D-stacked L2 cache on DVFS-enabled multi-core

Abstract

Three-dimensional integrated circuits (3D ICs) have the potential to reduce interconnect length and improve performance. However, high power density of 3D ICs incurs many temperature-related problems, especially leakage power dissipation which exponentially increases with temperature. In this paper, we propose a runtime power management technique for 3D multi-core system. The proposed method minimizes energy consumption of cores, cache, and off-chip memory by integrating dynamic voltage and frequency scaling (DVFS) and dynamic cache reconfiguration (DCR) in a temperature-aware manner without incurring performance penalty. Experimental results based on several benchmark programs: H.264 decoder, ray tracing, and SPEC2000 have shown that the proposed method yields up to 21% reduction in energy consumption compared to the existing method.