(A) high linear low 1/f noise 25% duty cycle LO I/Q mixer for FM radio receiver

Abstract

This thesis proposes a low power, low flicker noise and high IIP3 I/Q mixer for 76-108MHz EURO/US/Korea/Japan FM radio receiver applications is presented. Before explaining proposed I/Q mixer, the fundamental theory of mixer is summarized. The explanation of performance metrics of mixer and various mixer architectures are also included. The proposed I/Q mixer includes a trans-conductance (Gm) stage, a current mode passive mixer core driven by a 25% duty cycle LO, a trans-impedance amplifier (TIA), and a 25% duty cycle LO generator. By adopting gm” cancellation in the Gm stage and a 25% duty cycle LO in the switching stage, the proposed mixer achieves good linearity and significantly low 1/f noise with extremely low power consumption. Simulated in 65nm CMOS technology, the proposed mixer shows 23dB gain, 8.7dB DSB-NF, under 10kHz 1/f noise corner frequency, and 10dBm IIP3, respectively, while consuming 960uW from a 1.2V supply.