Phase-locked loop is often used in I/O interfaces of analog and digital integrated circuits to improve the overall system timing. In order to improve the overall system timing of I/O interfaces, the PLL having good jitter performance is necessary. The jitter performance can be improved by optimizing PLL’s loop bandwidth according to its noise performance. However, the equation of the bandwidth contains a gain of voltage controlled oscillator which is sensitive to process, voltage and temperature variation (PVT). Even though the optimum bandwidth is chosen in a PLL design, the bandwidth can be variable due to PVT variation. To maintain the optimum bandwidth in PLL design, a variable gain of VCO must be canceled out in the equation of bandwidth. In addition, damping factor and ratio of the bandwidth and the reference frequency must be constant even though the frequency range of reference clock is varied [1]. When the bandwidth can track the reference frequency regardless of $K_{DCO}$. This tracking in turn provides a robust design with respect to PVT variation. The one method to achieve PVT tolerant damping factor and the loop bandwidth is determining these two variables in terms of robust variables. These two variables are determined by ratio between two capacitances. Another technique sharing a bias current between blocks to cancel out the $K_{VCO}$ is reported [2]. The damping factor and the loop bandwidth are determined by a robust loop filter. Nowadays, all digital PLL, replacing the analog components with purely digital equivalents, is reported [3],[4],[5]. The digital phase locked loop has several advantages in comparison to the analog PLL: easy scalability with process shrink and PVT tolerance of digital circuits, and the inherent noise immunity of digital circuits, and the inherent noise immunity of digital circuits. However, the ADPLL also suffers from PVT variation due to its analog blocks, a time-to-digital converter and a digital-controlled oscillat...