DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 류승탁 | - |
dc.contributor.advisor | Ryu, Seung-Tak | - |
dc.contributor.author | 홍혁기 | - |
dc.contributor.author | Hong, Hyeok-Ki | - |
dc.date.accessioned | 2013-09-12T01:55:16Z | - |
dc.date.available | 2013-09-12T01:55:16Z | - |
dc.date.issued | 2012 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=486853&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/180702 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2012.2, [ v, 34p ] | - |
dc.language | kor | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | 아날로그디지털컨버터 | - |
dc.subject | ADC | - |
dc.subject | 2b/cycle | - |
dc.subject | Nonbinary | - |
dc.subject | Dynamic latch | - |
dc.subject | SAR ADC | - |
dc.title | Speed enhancement 기법을 포함하는 45nm 7b 1.1V 800MS/s, 1.25V 1GS/s nonbinary 2bit/cycle SAR ADC 의 설계 | - |
dc.title.alternative | A 45nm CMOS, 7-b, 1.1-V 800-MS/s, 1.25-V 1-GS/s, Nonbinary 2-b/cycle SAR ADC with Speed Enhancement Techniques | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 486853/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
dc.identifier.uid | 020103695 | - |
dc.contributor.localauthor | 류승탁 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.