Low-noise digital phase locked loop using reference multiplication with adaptive calibration

Abstract

Designing a low noise fractional-N digital phase locked loop (DPLL) is quite an issue these days. This paper also presents techniques for good noise performance of fractional-N DPLL. The technique includes increasing reference frequency for low phase noise. Increasing reference frequency reduces divide value. Also higher reference frequency increases operation frequency of delta-sigma modulator (DSM) which is one of the major noise source in fractional-N DPLL. These may lead to better noise performance of DPLL. If DPLL contains oversampling time to digital converter (TDC), increased reference frequency will alleviate its requirements. In order to increase reference frequency, integer-N type frequency synthesizer based on open loop scheme is implemented. This scheme can lower the phase noise caused by increasing reference frequency. However, it has static mismatch which can bring severe degradation of noise performance. Especially, it causes the reference spur. To solve this problem, benefit from digital scheme can be derived. By adopting adaptive filter, static noise caused by mismatch can be reduced. The proposed DPLL fabricated in 65nm CMOS process.