Design of a Low-Power and a Low-Noise Phase-Locked Loop저전력 저잡음 위상동기루프의 설계
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Cho, Seong-Hwan | - |
| dc.contributor.advisor | 조성환 | - |
| dc.contributor.author | Park, Dong-Min | - |
| dc.contributor.author | 박동민 | - |
| dc.date.accessioned | 2013-09-11T05:15:54Z | - |
| dc.date.available | 2013-09-11T05:15:54Z | - |
| dc.date.issued | 2011 | - |
| dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=482626&flag=dissertation | - |
| dc.identifier.uri | http://hdl.handle.net/10203/180244 | - |
| dc.description | 학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2011.8, [ vi, 69 p. ] | - |
| dc.language | eng | - |
| dc.publisher | 한국과학기술원 | - |
| dc.subject | PLL | - |
| dc.subject | low power | - |
| dc.subject | low noise | - |
| dc.subject | 위상동기루프 | - |
| dc.subject | 저전력 | - |
| dc.subject | 저잡음 | - |
| dc.subject | 전압제어발진기 | - |
| dc.subject | vco | - |
| dc.title | Design of a Low-Power and a Low-Noise Phase-Locked Loop | - |
| dc.title.alternative | 저전력 저잡음 위상동기루프의 설계 | - |
| dc.type | Thesis(Ph.D) | - |
| dc.identifier.CNRN | 482626/325007 | - |
| dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
| dc.identifier.uid | 020057207 | - |
| dc.contributor.localauthor | Cho, Seong-Hwan | - |
| dc.contributor.localauthor | 조성환 | - |
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- EE-Theses_Ph.D.(박사논문)
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