High-frequency scalable modeling of a through silicon via (TSV) and proposal of a failure detection method of 3D ICs

Abstract

In this dissertation, we propose a high-frequency scalable electrical model of a TSV. The proposed model includes not only TSV but also bump and re-distribution layer (RDL), which are additional components when using TSVs for 3D IC design. The proposed model is developed with analytic RLGC equations derived from the physical configuration of a TSV. Each analytic equation is proposed as a function of design parameters of a TSV, bump and RDL, which is to be scalable. As a result, single-ended signal TSV and differential signal TSV is analytically modeled with scalability. The scalability of the proposed model is verified by simulation from the 3D field solver with parameter variations, such as TSV diameter, pitch between TSVs and TSV height. The proposed model is experimentally validated by the measurement up to 20 GHz with the fabricated test vehicles of a single-ended and a differential TSV channel. Based on the proposed scalable model, we analyze and compare the electrical behaviors of a single-ended and a differential signal TSV, depending on the design parameter variations in frequency domain and time domain such as insertion loss, characteristic impedance, voltage/timing margin and noise immunity. In addition, power consumption modeling of a TSV channel which includes TSV depletion effect is proposed based on the verified scalable analytical model. With power consumption modeling, we analyze and compare power consumption depending on design variations and 3D architectures. For the wide-bandwidth 3D IC, a novel 3D IC reliability test and analysis method is proposed using the proposed analytical model. The proposed method which is to detect and differentiate TSV failures and failure locations are verified by measurements with fabricated test vehicles.