On-Chip electromagnetic bandgap structures for suppression of simultaneous switching noise cou-pling in on-chip power distribution networks

Abstract

During more than last thirty years, the silicon process has continuously scaled down to satisfy the market demand. However, because scaling down the silicon process has become more difficult as the gate length approaches tens of nanometers, vertically stacked three-dimensional ICs (3D-ICs) based on a through-silicon via (TSV) have been emerging for the next era as an alternative to traditional 2D silicon ICs. Since the TSV occupies relatively large area compared to a transistor, an IC at each tier is forced to share its power/ground TSVs to achieve as many signal TSVs as possible in the limited area. However, sharing the power/ground TSVs may cause many problems in the system. Simultaneous switching noise (SSN) from digital circuits can be easily coupled to other circuits in different tiers through shared power distribution networks (PDNs) because TSVs have extremely small parasitic effects. The SSN coupled to a noise-sensitive RF / analog circuit results in timing skew, jitter, sensitivity degradation, malfunction and etc. Previous methods to suppress the SSN coupling in package / board substrates are not capable to suppress the SSN coupling that internally exists in on-chip PDNs. Because the victim and aggressor are both existed in on-chip PDN and the current path via off-chip PDN is mostly blocked by the inductance of bond wire, thus, the suppression techniques in off-chip PDN cannot control the on-chip noise coupling. This gives rise to the need for the SSN coupling suppression method in a chip-level PDN. In this thesis, a new method to suppress the SSN coupling in chip-level PDNs is proposed. In chapter 1, research background and motivation are introduced. In chapter 2, three types of on-chip electromagnetic bandgap (EBG) structures are proposed and experimentally verified. For each proposed structure, cutoff frequency estimation is conducted based on a dispersion diagram analysis. The proposed inductor-MOS capacitor EBG (IM-EBG) structure is based on s...