A Binary-Weighted Switching and Reconfiguration-Based Programmable Gain Amplifier

Abstract

In previous works, the authors reported on binary-weighted switching and reconfiguration techniques to design programmable gain amplifiers (PGAs) with a wide decibel (dB)-linear range, a small gain error, a wide 3-dB bandwidth, and high linearity. In this brief, two techniques are analyzed in more detail. Adopting the two techniques, a new low-voltage PGA version is proposed that offers a precise and process/temperature- insensitive gain and achieves a double dB- linear range with a small gain error while maintaining the same chip size, as compared with those of previous designs. Implemented in 0.18-mu m CMOS, from the measurements, the proposed PGA shows a dB- linear gain range of 42 dB (-21 to 21 dB) with a gain error of less than +/- 0.54 dB, a maximum input-referred third-order intercept point (IIP3) of 14 dBm, and a 3-dB bandwidth of 60 MHz at the maximum gain while consuming only 2.1 mA from a 1.5-V supply.