Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns

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dc.contributor.authorKim, Bongjinko
dc.contributor.authorYoo, Injaeko
dc.contributor.authorPark, In-Cheolko
dc.date.accessioned2013-08-08T06:03:57Z-
dc.date.available2013-08-08T06:03:57Z-
dc.date.created2013-06-18-
dc.date.created2013-06-18-
dc.date.issued2013-03-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.60, no.3, pp.162 - 166-
dc.identifier.issn1549-7747-
dc.identifier.urihttp://hdl.handle.net/10203/174840-
dc.description.abstractIn this brief, we present how parallel-interleaved addresses generated by a quadratic permutation polynomial (QPP) interleaver are related to each other and propose a low-complexity parallel QPP interleaver based on the relationship. While a conventional parallel turbo decoder employs a number of interleavers as many as the parallel factor, the proposed method, which benefits from the arithmetic relationship denoted as the permutation pattern (PP), supports the parallel interleaving using only a single interleaver, resulting in a notable reduction of complexity. The strength of the proposed method stems from the fact that the PP is fully determined by only the decoding parameters, such as block size, parallel factor, and QPP coefficients. Experiment results on the Long Term Evolution turbo codes show that the proposed interleaver can significantly reduce the hardware complexity compared with conventional implementations.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectTHROUGHPUT TURBO-DECODER-
dc.subjectARCHITECTURE-
dc.subjectDESIGN-
dc.titleLow-Complexity Parallel QPP Interleaver Based on Permutation Patterns-
dc.typeArticle-
dc.identifier.wosid000318575100010-
dc.identifier.scopusid2-s2.0-84875364976-
dc.type.rimsART-
dc.citation.volume60-
dc.citation.issue3-
dc.citation.beginningpage162-
dc.citation.endingpage166-
dc.citation.publicationnameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS-
dc.identifier.doi10.1109/TCSII.2013.2240911-
dc.contributor.localauthorPark, In-Cheol-
dc.contributor.nonIdAuthorKim, Bongjin-
dc.contributor.nonIdAuthorYoo, Injae-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorParallel architecture-
dc.subject.keywordAuthorpermutation pattern (PP)-
dc.subject.keywordAuthorquadratic permutation polynomial (QPP) interleaver-
dc.subject.keywordAuthorturbo decoder-
dc.subject.keywordPlusTHROUGHPUT TURBO-DECODER-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusDESIGN-
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