A high-precision spread spectrum clock generator based on a fractional-N phase locked loop

Abstract

A low jitter Spread Spectrum Clock Generator (SSCG) based on a fractional-N Phase Locked Loop (PLL) capable of generating various Electromagnetic Interference (EMI) reduction levels is proposed. A digital compensation filter is fully integrated in the design to prevent various triangular modulation profiles from being distorted by the prohibitively small PLL loop bandwidth. A simple but comprehensive logic design included in the digital filter provides independently controllable modulation frequency, f (m), and modulation ratio, delta(m) within all modulation modes (up, down, center). The proposed SSCG is designed in a 0.18 mu m CMOS standard cell library and operates at 72 MHz with f (m) ranging from 58 to 112.5 kHz and delta(m) ranging from 0.75 to 2 %.