A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part I: Charge Model

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dc.contributor.authorDuarte, Juan Pabloko
dc.contributor.authorChoi, Sung-Jinko
dc.contributor.authorMoon, Dong-Ilko
dc.contributor.authorAhn, Jae-Hyukko
dc.contributor.authorKim, Jee-Yeonko
dc.contributor.authorKim, Sung-Hoko
dc.contributor.authorChoi, Yang-Kyuko
dc.date.accessioned2013-06-07T08:03:24Z-
dc.date.available2013-06-07T08:03:24Z-
dc.date.created2013-05-07-
dc.date.created2013-05-07-
dc.date.issued2013-02-
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.60, no.2, pp.840 - 847-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10203/173828-
dc.description.abstractA universal core model for multiple-gate field-effect transistors (Mug-FETs) is proposed. The proposed charge and drain current models are presented in Parts I and II, respectively. It is first demonstrated that an exact potential profile in the entire channel is not necessary for the derivation of accurate charge models in inversion-mode FETs. With application of this new concept, a universal charge model is derived for Mug-FETs by assuming an arbitrary channel potential profile, which simplifies the mathematical formulation. Thereafter, using the Pao-Sah integral, a drain current model is obtained from the charge model of Part I. The proposed model can be expressed as an explicit and continuous form for all operation regimes; therefore, it is well suited for compact modeling to support fast circuit simulations. The model shows good agreement with 2-D and 3-D numerical simulations for several multiple-gate structures, such as single-gate, double-gate, triple-gate, rectangular gate-all-around, and cylindrical gate-all-around FETs.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectEQUIVALENT OXIDE THICKNESS-
dc.subjectHIGH-KAPPA INSULATORS-
dc.subjectDRAIN-CURRENT MODEL-
dc.subjectSOI MOSFETS-
dc.subjectCOMPACT MODEL-
dc.subjectCHANNEL-
dc.subjectDESIGN-
dc.titleA Universal Core Model for Multiple-Gate Field-Effect Transistors. Part I: Charge Model-
dc.typeArticle-
dc.identifier.wosid000316817900045-
dc.identifier.scopusid2-s2.0-84872862554-
dc.type.rimsART-
dc.citation.volume60-
dc.citation.issue2-
dc.citation.beginningpage840-
dc.citation.endingpage847-
dc.citation.publicationnameIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.identifier.doi10.1109/TED.2012.2233478-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.contributor.nonIdAuthorDuarte, Juan Pablo-
dc.contributor.nonIdAuthorMoon, Dong-Il-
dc.contributor.nonIdAuthorKim, Jee-Yeon-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorCompact modeling-
dc.subject.keywordAuthorcylindrical gate-all-around FET (Cy-GAA-FET)-
dc.subject.keywordAuthordouble-gate FET (DG-FET)-
dc.subject.keywordAuthorFinFET-
dc.subject.keywordAuthormultiple-gate FET (Mug-FET)-
dc.subject.keywordAuthorPoisson&apos-
dc.subject.keywordAuthors equation-
dc.subject.keywordAuthorrectangular gate-all-around FET (Re-GAA-FET)-
dc.subject.keywordAuthorsemiconductor device modeling-
dc.subject.keywordAuthorsingle-gate FET (SG-FET)-
dc.subject.keywordAuthortriple-gate FET (TG-FET)-
dc.subject.keywordPlusEQUIVALENT OXIDE THICKNESS-
dc.subject.keywordPlusHIGH-KAPPA INSULATORS-
dc.subject.keywordPlusDRAIN-CURRENT MODEL-
dc.subject.keywordPlusSOI MOSFETS-
dc.subject.keywordPlusCOMPACT MODEL-
dc.subject.keywordPlusCHANNEL-
dc.subject.keywordPlusDESIGN-
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