DC Field | Value | Language |
---|---|---|
dc.contributor.author | Duarte, Juan Pablo | ko |
dc.contributor.author | Choi, Sung-Jin | ko |
dc.contributor.author | Moon, Dong-Il | ko |
dc.contributor.author | Ahn, Jae-Hyuk | ko |
dc.contributor.author | Kim, Jee-Yeon | ko |
dc.contributor.author | Kim, Sung-Ho | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2013-06-07T08:03:24Z | - |
dc.date.available | 2013-06-07T08:03:24Z | - |
dc.date.created | 2013-05-07 | - |
dc.date.created | 2013-05-07 | - |
dc.date.issued | 2013-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.60, no.2, pp.840 - 847 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/173828 | - |
dc.description.abstract | A universal core model for multiple-gate field-effect transistors (Mug-FETs) is proposed. The proposed charge and drain current models are presented in Parts I and II, respectively. It is first demonstrated that an exact potential profile in the entire channel is not necessary for the derivation of accurate charge models in inversion-mode FETs. With application of this new concept, a universal charge model is derived for Mug-FETs by assuming an arbitrary channel potential profile, which simplifies the mathematical formulation. Thereafter, using the Pao-Sah integral, a drain current model is obtained from the charge model of Part I. The proposed model can be expressed as an explicit and continuous form for all operation regimes; therefore, it is well suited for compact modeling to support fast circuit simulations. The model shows good agreement with 2-D and 3-D numerical simulations for several multiple-gate structures, such as single-gate, double-gate, triple-gate, rectangular gate-all-around, and cylindrical gate-all-around FETs. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | EQUIVALENT OXIDE THICKNESS | - |
dc.subject | HIGH-KAPPA INSULATORS | - |
dc.subject | DRAIN-CURRENT MODEL | - |
dc.subject | SOI MOSFETS | - |
dc.subject | COMPACT MODEL | - |
dc.subject | CHANNEL | - |
dc.subject | DESIGN | - |
dc.title | A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part I: Charge Model | - |
dc.type | Article | - |
dc.identifier.wosid | 000316817900045 | - |
dc.identifier.scopusid | 2-s2.0-84872862554 | - |
dc.type.rims | ART | - |
dc.citation.volume | 60 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 840 | - |
dc.citation.endingpage | 847 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2012.2233478 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Duarte, Juan Pablo | - |
dc.contributor.nonIdAuthor | Moon, Dong-Il | - |
dc.contributor.nonIdAuthor | Kim, Jee-Yeon | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Compact modeling | - |
dc.subject.keywordAuthor | cylindrical gate-all-around FET (Cy-GAA-FET) | - |
dc.subject.keywordAuthor | double-gate FET (DG-FET) | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | multiple-gate FET (Mug-FET) | - |
dc.subject.keywordAuthor | Poisson&apos | - |
dc.subject.keywordAuthor | s equation | - |
dc.subject.keywordAuthor | rectangular gate-all-around FET (Re-GAA-FET) | - |
dc.subject.keywordAuthor | semiconductor device modeling | - |
dc.subject.keywordAuthor | single-gate FET (SG-FET) | - |
dc.subject.keywordAuthor | triple-gate FET (TG-FET) | - |
dc.subject.keywordPlus | EQUIVALENT OXIDE THICKNESS | - |
dc.subject.keywordPlus | HIGH-KAPPA INSULATORS | - |
dc.subject.keywordPlus | DRAIN-CURRENT MODEL | - |
dc.subject.keywordPlus | SOI MOSFETS | - |
dc.subject.keywordPlus | COMPACT MODEL | - |
dc.subject.keywordPlus | CHANNEL | - |
dc.subject.keywordPlus | DESIGN | - |
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