In this paper, we propose a fast and accurate model of the vertical noise coupling from an on-chip switching-mode power supply (SMPS) to a low noise amplifier (LNA) in a stacked 3-D-IC. To achieve both speed and accuracy, the model is based on the analytic formulas of static R, L, and C parasitic extraction, and includes consideration of the phase difference in the on-chip inductors using a new iterative calculation method. The proposed model and the prediction of vertically coupled noise at the LNA output using the model are experimentally validated on a fabricated stacked 3-D-IC consisting of an on-chip SMPS and LNA. Good agreement with the measurements is confirmed in both the frequency domain and the time domain. The enhancements of the proposed model, including the broad model bandwidth (< 4 GHz) as good as 3-D EM solver and 99% reduction of the simulation elapsed time (2 s) from 3-D EM solver, are confirmed. This paper also analyzes: 1) the impact of vertical noise coupling on the RF signal gain performance of the LNA and 2) the impact of variation in the stacking configuration, location, and thickness of the stacked LNA on the vertical noise coupling using the proposed model. Based on the results of our analysis, this paper proposes and verifies an effective method to reduce the vertical noise coupling using the proposed model.