Concatenated BCH Codes for NAND Flash Memories

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In this work, we consider designing high-rate error-control systems for storage devices using MLC NAND flash memories. Traditional systems designed with either a single BCH code or multiple short BCH codes may suffer from high decoding complexity or rate loss due to limited error-correcting capability, respectively. Aiming at achieving a stronger error-correcting capability with much reduced complexity, we propose an error-control system using a concatenation of short BCH codes with iterative decoding strategies. The performance of the proposed coding scheme is thoroughly analyzed and evaluated with computer simulations and a semi-analytic way at a target page-error rate, 10−14, which confirms our claims: the proposed coding scheme achieves good error-performance and complexity tradeoffs as compared to the traditional schemes and is very favorable for implementation.
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IEEE ICC (International Conference on Communications), pp.2611 - 2616

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EE-Conference Papers(학술회의논문)
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