Concatenated BCH Codes for NAND Flash Memories

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 385
  • Download : 0
In this work, we consider designing high-rate error-control systems for storage devices using MLC NAND flash memories. Traditional systems designed with either a single BCH code or multiple short BCH codes may suffer from high decoding complexity or rate loss due to limited error-correcting capability, respectively. Aiming at achieving a stronger error-correcting capability with much reduced complexity, we propose an error-control system using a concatenation of short BCH codes with iterative decoding strategies. The performance of the proposed coding scheme is thoroughly analyzed and evaluated with computer simulations and a semi-analytic way at a target page-error rate, 10−14, which confirms our claims: the proposed coding scheme achieves good error-performance and complexity tradeoffs as compared to the traditional schemes and is very favorable for implementation.
Publisher
IEEE
Issue Date
2012-06
Language
ENG
Citation

IEEE ICC (International Conference on Communications), pp.2611 - 2616

URI
http://hdl.handle.net/10203/173313
Appears in Collection
EE-Conference Papers(학술회의논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0