Gate Delay Modeling for Static Timing Analysis of Body-Biased Circuits

Abstract

Body biasing is a well-known circuit technique to compensate for increasing process variations. A static body biasing, in which fixed amount of bias voltage is applied after chips are sorted out according to process corners, is a convenient and viable approach in ASIC designs. The key question in this approach is how we generate new gate delays without recharacterizing all the gates, which is expensive. We notice, for the first time, that the ratio of delay (of original gate and the gate after body biasing) from the time input starts to change to the time output crosses Vdd=2 can be regarded invariant, i.e. it is a function of input transition time and load capacitance, but not a function of gate type. Therefore, once the ratio is characterized using a sample gate such as an inverter, it can be used to derive delay of all the other gates. We also propose some refinement techniques to improve accuracy. Experiments with industrial 32-nm library indicate that the average error over re-characterization is about 4% with maximum error being 11%, when maximum body bias voltage is assumed. The errors decrease as smaller bias voltage is applied.