Mobility enhancement by planarization of ferroelectric gate dielectric in pentacene thin film transistor for nonvolatile memory

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Owing to light-weight, solution processablity, and flexibility, organic electronics is attracting candidate for future electronics. By material synthesis with various functional group and manipulation of solutbility, many new devices are available easily, which gives new challenge for fabrication and devices itself. To operate organic systems, nonvolatile memory devices are needed to store operation code and data. Among many memorial media including charge storage material and molecular structure change material, ferroelectric polymer will be dealt in this presentation. Unlike electrons/holes trap mechanism, ferroelectric polymer operates by dipoles rotation by external electric field. Also, ferroelectric polymer is air stable material [1] and molecular dipoles can be aligned easily by annealing above Curie temperature or by applying strong electric field. Ferroelectric memory devices are categorized to two types of devices. One is capacitive type memory and the other is transistor type. Capacitive type is very simple structure of metal/ferroelectric/metal (MFM). However, device scaling down makes signal detection interfered by noise signal because total charge stored in one capacitor reduces to noise level [1]. Vertical capacitor in dynamic random access memory (DRAM) was also invented to hinder such interference. However, transistor type can avoid the bottle neck by integrating current passing through source and drain [1]. In this presentation, transistor type memory will be discussed. To fabricate ferroelectric gated transistor, bottom-gate and top-contact structure was selected. Al was deposited as gate electrode. To form ferroelectric gate dielectric, poly(vinylidene fluoride – trifluoroethylene), P(VDF-TrFE), was spin coated on Al gate. P(VDF-TrFE) is a representative ferroelectric polymer with highest remanent polarization (~10uC/cm2) and superior endurance (>107) [2] and long retention time (>10 yr.) [3]. P(VDF-TrFE) is crystal polymer so the crystallinity can induce surface roughness after spin coating and annealing process. This surface roughness in transistor type memory severely affects carrier mobility when channel arises [4]. For mobility enhancement, surface planarization is required. To reduce surface roughness, spin coating method was manipulated from solubility modulation by mixing of orthogonal solvent. It was found that solubility could be changed just by ethyl alcohol addition. By solubility modulation, double spin coating could be feasible and the surface roughness also changed as shown in Table 1. To form active layer, pentacene was evaporated in vacuum. Finally, source and drain electrode of Au were evaporated. All patterns were formed by shadow mask. And electrical measurements were performed in room temperature and N2 atmosphere. Figure 1 shows the final device structure scheme and Figure 2 shows the VG-ID characteristics of a rough device (single coating) and a smooth device (double coating). Fast mobility in nonvolatile memory device can make drain bias small in read operation, signal charge large and gate bias small in write operation as shown in Fig.2.
Publisher
Korea Photonics Technology Institute
Issue Date
2012-11-08
Language
ENG
Citation

International Conference on Nano Science and Nano Technology

URI
http://hdl.handle.net/10203/173105
Appears in Collection
EE-Conference Papers(학술회의논문)
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