A 7b, 3.75ps Resolution Two-Step Time-to-Digital Converter in 65nm CMOS Using Pulse-Train Time Amplifier

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Publisher
IEEE
Issue Date
2012-06-15
Language
English
Citation

2012 IEEE Symposia on VLSI Technology and Circuits, pp.192 - 193

URI
http://hdl.handle.net/10203/170718
Appears in Collection
EE-Conference Papers(학술회의논문)

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