DSpace at KOASAS: A chip scale wafer level packaging for LED using surface aligning technique

DSpace at KOASAS

College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

A chip scale wafer level packaging for LED using surface aligning technique

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Kim, Jin Kwan / Lee, Hee Chul researcher

Issue Date: 2012-06

Language: ENG

Citation: AWAD, 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices

URI: http://hdl.handle.net/10203/170516

Appears in Collection: EE-Conference Papers(학술회의논문)

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