Field Effect Transistor With A Physical Gap Graphene Channel For Digital Logic Device With High On/Off Current Ratio
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Mun, Jeong Hun | - |
| dc.contributor.author | Cho, Byung Jin | - |
| dc.date.accessioned | 2013-03-29T10:25:20Z | - |
| dc.date.available | 2013-03-29T10:25:20Z | - |
| dc.date.created | 2012-07-05 | - |
| dc.date.issued | 2011-05 | - |
| dc.identifier.citation | Nature conference - Graphene : The Road to Applications, v., no., pp. - | - |
| dc.identifier.uri | http://hdl.handle.net/10203/170049 | - |
| dc.language | ENG | - |
| dc.publisher | Nature Publishing Group | - |
| dc.title | Field Effect Transistor With A Physical Gap Graphene Channel For Digital Logic Device With High On/Off Current Ratio | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | Nature conference - Graphene : The Road to Applications | - |
| dc.identifier.conferencecountry | United States | - |
| dc.contributor.localauthor | Cho, Byung Jin | - |
| dc.contributor.nonIdAuthor | Mun, Jeong Hun | - |
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