Integration of cache data allocation and voltage/frequency scaling for temperature-constrained multi-core systems with 3-D stacked cache memory

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dc.contributor.authorKyung, Chong-Minko
dc.contributor.authorKang, Kyungsuko
dc.contributor.authorJung, Jongpilko
dc.contributor.authorYoo, Sungjooko
dc.date.accessioned2013-03-29T09:09:27Z-
dc.date.available2013-03-29T09:09:27Z-
dc.date.created2012-07-03-
dc.date.created2012-07-03-
dc.date.created2012-07-03-
dc.date.issued2011-08-09-
dc.identifier.citationThe 54th International Midwest Symposium on Circuits and Systems (MWSCAS)-
dc.identifier.urihttp://hdl.handle.net/10203/169646-
dc.languageEnglish-
dc.publisher123-
dc.titleIntegration of cache data allocation and voltage/frequency scaling for temperature-constrained multi-core systems with 3-D stacked cache memory-
dc.typeConference-
dc.identifier.wosid000296057200219-
dc.identifier.scopusid2-s2.0-80053653061-
dc.type.rimsCONF-
dc.citation.publicationnameThe 54th International Midwest Symposium on Circuits and Systems (MWSCAS)-
dc.identifier.conferencecountryKO-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.nonIdAuthorKang, Kyungsu-
dc.contributor.nonIdAuthorJung, Jongpil-
dc.contributor.nonIdAuthorYoo, Sungjoo-
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EE-Conference Papers(학술회의논문)
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