DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chung, Sang-Hye | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2013-03-29T07:45:14Z | - |
dc.date.available | 2013-03-29T07:45:14Z | - |
dc.date.created | 2012-06-21 | - |
dc.date.created | 2012-06-21 | - |
dc.date.issued | 2012-06-15 | - |
dc.identifier.citation | 2012 IEEE Symposium on VLSI Circuits | - |
dc.identifier.uri | http://hdl.handle.net/10203/169137 | - |
dc.description.abstract | This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the number of clock channels and the achievable data rate due to the lack of the jitter correlation between data and clock. Moreover, PSIJ due to a long clock distribution network and an injection-locked oscillator reduces the jitter correlation further. The proposed receiver eases this tradeoff, and also increases the jitter correlation reduced by PSIJ. The test chip achieves 9.6Gb/s with 1.22mW/Gb/s and occupies only 0.017mm2 in 65nm CMOS. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A 1.22mW/Gb/s 9.6Gb/s Data Jitter Mixing Forwarded-Clock Receiver Robust against Power Noise with 1.92ns Latency Mismatch between Data and Clock in 65nm CMOS | - |
dc.type | Conference | - |
dc.identifier.scopusid | 2-s2.0-84866599588 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 2012 IEEE Symposium on VLSI Circuits | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | Hawaii | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Chung, Sang-Hye | - |
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