Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Paik, S | ko |
| dc.contributor.author | Nam, GJ | ko |
| dc.contributor.author | Shin, Youngsoo | ko |
| dc.date.accessioned | 2013-03-29T07:03:33Z | - |
| dc.date.available | 2013-03-29T07:03:33Z | - |
| dc.date.created | 2012-06-01 | - |
| dc.date.created | 2012-06-01 | - |
| dc.date.created | 2012-06-01 | - |
| dc.date.issued | 2011-11-09 | - |
| dc.identifier.citation | International Conference on Computer-Aided Design (ICCAD), pp.640 - 646 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/168889 | - |
| dc.language | English | - |
| dc.publisher | IEEE/ACM | - |
| dc.title | Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000299009100100 | - |
| dc.identifier.scopusid | 2-s2.0-84855808128 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 640 | - |
| dc.citation.endingpage | 646 | - |
| dc.citation.publicationname | International Conference on Computer-Aided Design (ICCAD) | - |
| dc.identifier.conferencecountry | US | - |
| dc.contributor.localauthor | Shin, Youngsoo | - |
| dc.contributor.nonIdAuthor | Paik, S | - |
| dc.contributor.nonIdAuthor | Nam, GJ | - |
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