A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Oh, J. | - |
| dc.contributor.author | Park, J. | - |
| dc.contributor.author | Kim, G. | - |
| dc.contributor.author | Lee, S. | - |
| dc.contributor.author | Yoo, Hoi-Jun | - |
| dc.date.accessioned | 2013-03-29T06:41:36Z | - |
| dc.date.available | 2013-03-29T06:41:36Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2011-02-20 | - |
| dc.identifier.citation | 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, v., no., pp.130 - 131 | - |
| dc.identifier.issn | 0193-6530 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/168738 | - |
| dc.language | ENG | - |
| dc.publisher | IEEE | - |
| dc.title | A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-79955726604 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 130 | - |
| dc.citation.endingpage | 131 | - |
| dc.citation.publicationname | 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 | - |
| dc.identifier.conferencecountry | United States | - |
| dc.identifier.conferencecountry | United States | - |
| dc.contributor.localauthor | Yoo, Hoi-Jun | - |
| dc.contributor.nonIdAuthor | Oh, J. | - |
| dc.contributor.nonIdAuthor | Park, J. | - |
| dc.contributor.nonIdAuthor | Kim, G. | - |
| dc.contributor.nonIdAuthor | Lee, S. | - |
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