A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor

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dc.contributor.authorOh, J.-
dc.contributor.authorPark, J.-
dc.contributor.authorKim, G.-
dc.contributor.authorLee, S.-
dc.contributor.authorYoo, Hoi-Jun-
dc.date.accessioned2013-03-29T06:41:36Z-
dc.date.available2013-03-29T06:41:36Z-
dc.date.created2012-02-06-
dc.date.issued2011-02-20-
dc.identifier.citation2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, v., no., pp.130 - 131-
dc.identifier.issn0193-6530-
dc.identifier.urihttp://hdl.handle.net/10203/168738-
dc.languageENG-
dc.publisherIEEE-
dc.titleA 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor-
dc.typeConference-
dc.identifier.scopusid2-s2.0-79955726604-
dc.type.rimsCONF-
dc.citation.beginningpage130-
dc.citation.endingpage131-
dc.citation.publicationname2011 IEEE International Solid-State Circuits Conference, ISSCC 2011-
dc.identifier.conferencecountryUnited States-
dc.identifier.conferencecountryUnited States-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.nonIdAuthorOh, J.-
dc.contributor.nonIdAuthorPark, J.-
dc.contributor.nonIdAuthorKim, G.-
dc.contributor.nonIdAuthorLee, S.-
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EE-Conference Papers(학술회의논문)
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