On-chip network design considerations for compute accelerators
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Bakhoda A. | - |
| dc.contributor.author | Kim, John Dongjun | - |
| dc.contributor.author | Aamodt T.M. | - |
| dc.date.accessioned | 2013-03-28T20:20:12Z | - |
| dc.date.available | 2013-03-28T20:20:12Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2010-09-11 | - |
| dc.identifier.citation | 19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, v.0, no.0, pp.535 - 536 | - |
| dc.identifier.issn | 1089-795X | - |
| dc.identifier.uri | http://hdl.handle.net/10203/167067 | - |
| dc.language | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | On-chip network design considerations for compute accelerators | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-78149252728 | - |
| dc.type.rims | CONF | - |
| dc.citation.volume | 0 | - |
| dc.citation.issue | 0 | - |
| dc.citation.beginningpage | 535 | - |
| dc.citation.endingpage | 536 | - |
| dc.citation.publicationname | 19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010 | - |
| dc.identifier.conferencecountry | Austria | - |
| dc.identifier.conferencecountry | Austria | - |
| dc.contributor.localauthor | Kim, John Dongjun | - |
| dc.contributor.nonIdAuthor | Bakhoda A. | - |
| dc.contributor.nonIdAuthor | Aamodt T.M. | - |
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