Pulsed-latch aware placement for timing-integrity optimization
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Chuang, Y.-L. | ko |
| dc.contributor.author | Kim, S. | ko |
| dc.contributor.author | Shin, Youngsoo | ko |
| dc.contributor.author | Chang, Y.-W. | ko |
| dc.date.accessioned | 2013-03-28T11:12:32Z | - |
| dc.date.available | 2013-03-28T11:12:32Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2010-06-13 | - |
| dc.identifier.citation | 47th Design Automation Conference, DAC '10, pp.280 - 285 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/165162 | - |
| dc.language | English | - |
| dc.publisher | DAC '10 | - |
| dc.title | Pulsed-latch aware placement for timing-integrity optimization | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000409973500054 | - |
| dc.identifier.scopusid | 2-s2.0-77956219273 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 280 | - |
| dc.citation.endingpage | 285 | - |
| dc.citation.publicationname | 47th Design Automation Conference, DAC '10 | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | Anaheim, CA | - |
| dc.contributor.localauthor | Shin, Youngsoo | - |
| dc.contributor.nonIdAuthor | Chuang, Y.-L. | - |
| dc.contributor.nonIdAuthor | Kim, S. | - |
| dc.contributor.nonIdAuthor | Chang, Y.-W. | - |
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