A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, W. | ko |
| dc.contributor.author | Ryu, C. | ko |
| dc.contributor.author | Cho, J. | ko |
| dc.contributor.author | Song, E. | ko |
| dc.contributor.author | Kim, Joungho | ko |
| dc.date.accessioned | 2013-03-28T08:09:34Z | - |
| dc.date.available | 2013-03-28T08:09:34Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2010-04-12 | - |
| dc.identifier.citation | 2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010, pp.334 - 337 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/164029 | - |
| dc.language | English | - |
| dc.publisher | APEMC 2010 | - |
| dc.title | A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000397213100085 | - |
| dc.identifier.scopusid | 2-s2.0-77954979943 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 334 | - |
| dc.citation.endingpage | 337 | - |
| dc.citation.publicationname | 2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010 | - |
| dc.identifier.conferencecountry | CC | - |
| dc.identifier.conferencelocation | Beijing | - |
| dc.contributor.localauthor | Kim, Joungho | - |
| dc.contributor.nonIdAuthor | Lee, W. | - |
| dc.contributor.nonIdAuthor | Ryu, C. | - |
| dc.contributor.nonIdAuthor | Cho, J. | - |
| dc.contributor.nonIdAuthor | Song, E. | - |
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