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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

A 10 bit piecewise linear cascade interpolation DAC with loop gain ratio control

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dc.contributor.authorLee, S.ko
dc.contributor.authorKim, K.ko
dc.contributor.authorPark, K.ko
dc.contributor.authorPark, C.ko
dc.contributor.authorLee, B.ko
dc.contributor.authorJeon, J.ko
dc.contributor.authorHuh, J.ko
dc.contributor.authorYang, J.ko
dc.contributor.authorKim, H.ko
dc.contributor.authorCho, Gyu-Hyeongko
dc.date.accessioned2013-03-28T08:02:57Z-
dc.date.available2013-03-28T08:02:57Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2010-09-19-
dc.identifier.citation32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010-
dc.identifier.issn0886-5930-
dc.identifier.urihttp://hdl.handle.net/10203/163991-
dc.languageEnglish-
dc.publisherCICC 2010-
dc.titleA 10 bit piecewise linear cascade interpolation DAC with loop gain ratio control-
dc.typeConference-
dc.identifier.wosid000287027300076-
dc.identifier.scopusid2-s2.0-78649842926-
dc.type.rimsCONF-
dc.citation.publicationname32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationSan Jose, CA-
dc.contributor.localauthorCho, Gyu-Hyeong-
dc.contributor.nonIdAuthorLee, S.-
dc.contributor.nonIdAuthorKim, K.-
dc.contributor.nonIdAuthorPark, K.-
dc.contributor.nonIdAuthorPark, C.-
dc.contributor.nonIdAuthorLee, B.-
dc.contributor.nonIdAuthorJeon, J.-
dc.contributor.nonIdAuthorHuh, J.-
dc.contributor.nonIdAuthorYang, J.-
dc.contributor.nonIdAuthorKim, H.-
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EE-Conference Papers(학술회의논문)
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