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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Multi-Stacking Through-Silicon-Via Effects on Signal Integrity and Power Integrity for Application of 3-Dimensional Stacked-Chip-Package

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dc.contributor.authorKim, Joungho-
dc.contributor.authorPak, Jun So-
dc.contributor.authorRyu, Chunghyun-
dc.date.accessioned2013-03-28T06:50:49Z-
dc.date.available2013-03-28T06:50:49Z-
dc.date.created2012-02-06-
dc.date.issued2008-
dc.identifier.citationPresented at XXIX General Assembly of International Union of Radio Science (URSIGA 2008), v., no., pp. --
dc.identifier.urihttp://hdl.handle.net/10203/163653-
dc.languageENG-
dc.titleMulti-Stacking Through-Silicon-Via Effects on Signal Integrity and Power Integrity for Application of 3-Dimensional Stacked-Chip-Package-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationnamePresented at XXIX General Assembly of International Union of Radio Science (URSIGA 2008)-
dc.identifier.conferencecountryUnited States-
dc.identifier.conferencecountryUnited States-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorPak, Jun So-
dc.contributor.nonIdAuthorRyu, Chunghyun-
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EE-Conference Papers(학술회의논문)
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