A hold-up time compensation circuit for PWM front-end DC/DC converters

Abstract

A hold-up time compensation circuit is proposed to get high efficiency of the front-end dc-dc converter. The proposed circuit can make the front-end dc-dc converter built with 0.5 duty ratio so that the conduction loss of the primary side and voltage stress across rectifier in the secondary side are reduced and the higher efficiency can be obtained. Furthermore, the requirement of an output filter significantly can diminish due to the perfect filtered waveform. A 12 V/100A prototype has been made and experimental results are given to verify the theoretic analysis and detailed features.