Fabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowireFabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowire
- Issue Date
- 2007-05-06
- Language
- ENG
- Citation
211th Electrochemical Society Meeting, pp.0 - 0
- Appears in Collection
- EE-Conference Papers(학술회의논문)
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