Reducing transaction-level modeling effort while retaining low communication overhead for HW/SW co-emulation system

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Issue Date
2007-04-25
Language
ENG
Citation

2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007

URI
http://hdl.handle.net/10203/157259
Appears in Collection
EE-Conference Papers(학술회의논문)
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