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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

An estimation method of chip level power distribution network inductance using full wave simulation and segmentation method

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dc.contributor.authorKim, J.-
dc.contributor.authorShim, J.-
dc.contributor.authorLee, W.-
dc.contributor.authorPak, J.S.-
dc.contributor.authorKim, Joungho-
dc.date.accessioned2013-03-26T01:11:36Z-
dc.date.available2013-03-26T01:11:36Z-
dc.date.created2012-02-06-
dc.date.issued2008-05-19-
dc.identifier.citation2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, v., no., pp.339 - 342-
dc.identifier.urihttp://hdl.handle.net/10203/156659-
dc.languageENG-
dc.titleAn estimation method of chip level power distribution network inductance using full wave simulation and segmentation method-
dc.typeConference-
dc.identifier.scopusid2-s2.0-51749089360-
dc.type.rimsCONF-
dc.citation.beginningpage339-
dc.citation.endingpage342-
dc.citation.publicationname2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008-
dc.identifier.conferencecountrySingapore-
dc.identifier.conferencecountrySingapore-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorKim, J.-
dc.contributor.nonIdAuthorShim, J.-
dc.contributor.nonIdAuthorLee, W.-
dc.contributor.nonIdAuthorPak, J.S.-
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EE-Conference Papers(학술회의논문)
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