A 900-mV area-efficient source-degenerated CMOS four-quadrant multiplier with 10.6-GHz bandwidth

Abstract

This paper presents a low-voltage area-efficient four-quadrant CMOS multiplier reconfigured in a sourcedegenerated topology and designed as a part of a correlator for an integrated ultra-wideband (UWB) transceiver. The simulation based on a 0.18-μ m CMOS technology shows that the multiplier offers 10.6-GHz bandwidth while dissipating 290 μ A from a 0.9-V supply.