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Due-date based algorithm for order-lot pegging in a semiconductor wafer fabrication Facility = 반도체 생산 공정에서 납기를 고려한 오더-랏 결합 방법에 관한 연구link An, Kwee-Yeong; 안귀연; et al, 한국과학기술원, 2005 |
Minimizing total tardiness in a two-machine flowshop scheduling problem with availability constraint on the first machine Lee, Ju-Yong; Kim, Yeong-Dae, COMPUTERS & INDUSTRIAL ENGINEERING, v.114, pp.22 - 30, 2017-12 |
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